The work “Wafer Level 3-D ICs Process Technology,” C. S. Tan et al., editors, pp. 197-217, presents a review of 3D technology. It discloses a bonding process comprising deposition of a bonding layer at low temperature and degassing annealing of this oxide at a temperature above the deposition temperature of this oxide. When this technique is used, the presence of defects at the bonding interface is observed. In turn, these defects may adversely affect the bonding energy. Therefore, the problem arises of finding a novel process for achieving the assembly of two elements, via bonding layers, at low temperature.